Field of the Invention
The invention relates to a method for minimizing a layout area of an integrated circuit (IC), and more particularly to a method for minimizing a layout area of an IC to co-optimize channel routing and partition re-shaping.
Description of the Related Art
In recent years, the developing process of integrated circuits (ICs) such as super larger scale integrated circuits (LSIs) generally utilizes computer assisted design (CAD). According to such a developing process based on CAD, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip.
Before the IC chips are manufactured (or implemented), the floor plans and the layout areas of the IC chips are considered first so as to determine a die size of each IC chip. In general, the die size will affect the manufacturing cost for the IC chip. Therefore, it is desirable to optimize the floor plan of an IC chip for minimizing the layout area of the IC chip.